The present invention relates generally to computer devices and memory management systems thereof that employ a translation look-aside buffer (TLB), and particularly to a system and method for optimizing page entries in a TLB.
Organizing memory into pages is useful in that it allows the computer system to address memory by virtual addresses, with components such as the TLB able to map the virtual addresses to physical addresses stored in memory. This allows the computer system to address more memory than is physically available.
One limiting property of page entries in a TLB is that, for a given page size, the page start address must be aligned to the page size. This is problematic when using a mix of small and large page sizes because it requires that either the large pages are adjacent to one another, or that the “gaps” between large pages are filled in with numerous smaller pages. This, in turn, requires using more TLB page entries to define a large, contiguous range of memory that is subject to translation. For example, if only 64KB page entries are available, then 16 individual 64KB page entries are required to form a contiguous 1MB page entry.
Thus, there is a need in the art for a system and method for optimizing page entries in a TLB. The system and method allows a mix of page sizes to exist together in one contiguous area of memory while reducing the number of page entries in the TLB.